Advanced interconnect systems currently require extensive use of liners, glue layers and barrier layers. Titanium (Ti) and titanium nitride (TiN) thin films are used for providing such layers to facilitate the integration of tungsten (W) and aluminum (Al) filled plugs for contacts and vias. Plug aspect ratios of 2:1-3:1 will be needed for 0.25 and 0.18 micron CMOS logic technologies at sub 0.4 micron and 0.3 micron diameters, respectively. At these geometries, the demands on the step coverage of these films is increased considerably. At and beyond 0.25 micron technology, conventional Physical Vapor Deposition (PVD) of TiN is limited by step coverage. Several alternative processes to address these issues have been investigated, leading to considerable advances in Chemical Vapor Deposition (CVD) of TiN and collimated sputtering of TiN. Chemical Vapor Deposition of TiN can provide excellent step coverage. However, typically these processes require relatively high deposition temperatures and impurities such as carbon or halides from the precursors are often incorporated in the film.
In current CMOS processes, Ti and TiN films are deposited by Physical Vapor Deposition (PVD) using magnetron sputtering. The use of PVD provides excellent film properties at high purities and low defect densities. Thus, it is preferable and cost-effective to extend the capabilities of PVD processes as far as possible.
In the case of Ti films, this has been previously achieved by collimated PVD. However, the collimator approach for TiN has not been as successful due to defect problems. In particular, the TiN film deposited on the collimator surfaces does not adhere well to the surfaces and is a source for particle generation. A further disadvantage of the collimator approach is a reduced and variable deposition rate during the collimator life due to deposition of the film on the collimator.
PVD TiN is widely used for liner and glue layer applications in production of 0.35 micron generation products. Standard PVD TiN, however, does not have adequate bottom coverage, limiting its use beyond 0.25 micron technology. Once an overhang adjacent a via becomes appreciable, it further shadows the deposition on the sidewalls and bottom corners. Thus, simply using thicker deposited film cannot get around this problem. Thicker TiN also introduces several other problems--(i) the overhang at the via top makes W via fill more difficult; (ii) the thinning of the TiN just below the overhang creates a potential weak spot; and (iii) the thicker TiN dimensions over the field leads to a thicker metal stack height.
In previous technologies, the via profile was sloped slightly to accommodate the TiN overhang. This approach cannot be extended as design rules shrink and via to adjacent metal spacing becomes very small (i.e., .about.0.3 micron). The space of 0.3 micron has to accommodate overlay misalignment and the critical dimension variation in the via and metal patterns. Such requires via profiles to be vertical. The second problem listed above can lead to catastrophic failures. Here, the barrier TiN layer may fail just below the overhang, leading to a reaction between Ti and WF.sub.6 during CVD W deposition.
The W material deposited on the field area is normally removed by either CMP or by plasma etch. In the case where CMP is used, the use of thicker TiN requires a longer CMP polish step thereby reducing throughput. In the case where plasma W etch is used, the thicker TiN also results in a thicker metal stack for the next metal layer. A thicker metal stack makes it more difficult to achieve adequate gap fill at minimum spaces. More importantly, it results in increased sidewall capacitance. Such increased capacitance degrades the interconnect performance--both in terms of interconnect speed and crosstalk.
Referring to conventional sputtering deposition technologies, neutral metal atoms are emitted from the target in a roughly cosine distribution. This distribution coupled with the optimization of the sputtered source area is designed to result in a uniform thin film deposition on the substrate. This coupled with some gas scattering results in the metal atoms arriving at the substrate at a large angular distribution. This angular range manifests itself in varying deposition rate and film thickness uniformity dependent on the target to substrate spacing. It is also the primary reason for poor step coverage inasmuch as the field area has a large solid angle of view of the target, while the via sidewall and bottom have only a limited view.
Therefore, Ion Metal Plasma Physical Vapor Deposition (IMP PVD) has been utilized to improve bottom coverage of vias compared with conventional sputtering techniques. For example, in conventional sputtering techniques, the thickness of the material deposited at the base or bottom surface of the contact is typically 10% of the thickness of the material deposited atop horizontal surfaces outside of the contact area. However, with the utilization of IMP PVD, the thickness of the material deposited at the base or bottom surface of the contact is typically 30-40% of the thickness of the material deposited atop horizontal surfaces outside of the via or contact area.
A significant percentage of the neutral atoms emitted by the source are ionized by a radio frequency (RF) plasma generated between the source and the substrate in IMP PVD. These metal ions arrive at the semiconductor workpiece or wafer at a normal incidence resulting in substantial improvement in the bottom coverage of the via opening. The sidewall coverage is significantly reduced due to the arrival of the metal ions at a normal incidence.
It has been observed that IMP PVD of TiN typically provides sufficient bottom coverage in the center of the bottom surface of the via. However, the coverage at corners defined by the bottom surface and the sidewalls of the via is relatively thin compared with the coverage at the center region of the bottom surface of the via.
Therefore, there exists a need to provide adequate layer coverage adjacent the corners defined by the sidewalls and bottom surface of the via formed within the semiconductor device.